1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device including a source strapping line that electrically connects a plurality of cell sources for a signal input.
2. Description of the Related Art
A semiconductor memory device generally includes a plurality of transistors with source regions and drain regions. Additionally, the semiconductor memory device includes a source strapping line that connects the source regions of the plurality of transistors in a predetermined manner to facilitate the input of external signals (e.g., a ground voltage, etc.) Specifically, the source strapping line is disposed on a semiconductor substrate in predetermined intervals. By disposing the source strapping in predetermined intervals, the number of contacts for source strapping are minimized. Furthermore, the predetermined interval based disposition of the source strapping also improves the degree of integration in a device.
FIG. 1A is a plan view of a conventional semiconductor device. FIG. 1B is a sectional view taken along line I-I′ of FIG. 1A. Referring to FIGS. 1A and 1B, a device isolation layer is formed on a semiconductor substrate 10 to define a plurality of first active regions 14. In addition, source strapping active regions 16 are regularly disposed between the plurality of first active regions 14. The semiconductor device also includes a plurality of word lines 18. The plurality of word lines 18 cross over the tops of the first active regions 14 and the source strapping active regions 16. In addition, a drain region 20d is formed on an active region in one direction of each word line 18 and a source region 20s is formed on an active region in the other direction. Furthermore, a bit line contact 26d is connected to the drain region 20d. The source regions 20s formed in one direction of the word line 18 are electrically connected to the first active regions 14 and the second active regions 15 crossing over the source strapping active regions 16. Because the source regions 20s cross over the source strapping active regions 16, a source contact 26s is connected to the source strapping active regions 16 crossing over the second active regions 15.
As illustrated in FIGS. 1A and 1B, the word lines 18 of a conventional semiconductor device are bent in shape when passing on the source strapping active regions 16 to obtain an overlay margin of the source contact 26s and a bit line contact 26d. Additionally, the widths of the source strapping active regions 16 are formed to be wider than that of the first active regions 14. This increase in width is to minimize any influence that the source strapping active regions 16 may have on the cell transistor adjacent to source strapping active regions 16 in terms of affecting the characteristics of the semiconductor memory device.
A bit line 28 is formed to cross over the tops of the word lines 18 and be parallel to the first active regions 14. In addition, a source strapping line 30 is formed on the source strapping active regions 16 to cross over the tops of the word lines 18 and be parallel to the source strapping active regions 16. The bit line 28 is connected to the bit line contacts 26d there below, and the source strapping line 30 is connected to the source contacts 26s therebelow. In particular, the bit line 28 and the source strapping line 30 are formed on a first interlayer insulation layer 24 covering the word lines 18 and the bit line contact 26d. In addition, the source contacts 26s are formed through the first interlayer insulation layer 24.
In addition to word lines 18, the conventional semiconductor memory device also includes dummy word lines 18d. Specifically, dummy word lines 18d are disposed parallel to the word lines 18 in an outer perimeter of the word lines 18. The dummy word lines 18d are not used in an operation of a semiconductor device. Instead, the dummy word lines 18d are formed to prevent the word lines 18 from being inadvertently altered during the operation of the semiconductor device.
In a NOR non-volatile memory device, the source strapping line 30 is grounded. Accordingly, a ground line 40 is required to connect the source strapping line 30 to ground. In particular, the ground line 40 is electrically connected to a plurality of source strapping lines 30. Specifically, the source strapping lines 30 are covered with a second interlayer insulation layer 32. In addition, a strapping contact 34 is connected to the source strapping lines 30 through the second interlayer insulation layer 32. The ground line 40 is formed on the second interlayer insulation layer 32 to be electrically connected to the source strapping lines 30 through the strapping contact 34.
While the conventional semiconductor device includes a source strapping line to connect all the sources in the device, the conventional semiconductor device has many shortcomings. For example, as illustrated in FIGS. 1A and 1B, a conventional semiconductor device includes a source strapping active region 16 that is wider than other active regions so as to allow a source region to be grounded. However, a pitch change of the active regions due to a line width of the source strapping active region 16 may cause a change in the form of the first active regions 14 adjacent to the source strapping active region 16. In addition, the source strapping active region 16 may affect the normal operating characteristics of a cell transistor adjacent to the source strapping region 16.
In addition to the pitch change of the active region, a first wiring layer including the bit line 28 and the source strapping line 30 has an irregular pitch because of the source strapping line 30. The irregular pitch of the first wiring layer may inadvertently transform the bit line 28 that is adjacent to the source strapping line 30.
While the width of the source strapping active region 16 is formed with the minimum line width like another first active region 14, an interval between the source strapping active region 16 and the first active region 14 needs to be wider than an interval between the first active regions 14. By having a larger interval between the source strapping active region 16 and the first active region 14, changes to the characteristics of a cell transistor due to transformations in the word line 18 can be prevented. Similarly, even though the source strapping line 30 and the bit line 28 are formed with an identical line width, an interval between the bit line 28 and the source strapping line 30 needs to be wider than an interval between the bit lines 28. Additionally, when the source strapping line 30 is formed with the minimum line width like the bit line 28, an alignment margin of the strapping contact 34, which connects the source strapping line 30 and the ground line 40, needs to be maintained strictly.
The present disclosure is directed towards overcoming one or more of the problems associated with the conventional semiconductor devices.